A number of architectures exist for high-speed analog-to-digital (A/D) converters. For example, flash A/D converters use a plurality of components such as comparators that act in parallel to convert an analog signal into a digitized signal. Because these components all act simultaneously, flash A/D converters can achieve relatively high processing speeds. However, the number of comparators required for a flash A/D goes up exponentially with the bit size—e.g., a 10-bit flash A/D requires 210 (1024) comparators, thereby requiring a relatively large circuit area and accompanying power demands. As an alternative, a pipelined architecture would use just one stage per bit. However, coordinating the pipelining through each stage at high throughput rates becomes problematic.
Subranging A/D converters combine the parallel processing and pipelining features of the two architectures just discussed. A conventional subranging two-stage N-bit A/D converter 100 is shown in FIG. 1. A voltage-switching sample-and-hold circuit samples an input signal voltage Vin using a voltage switch driven according to a clock signal. When the voltage switch is closed, the voltage on capacitor C rises to match Vin. Conversely, when the voltage switch is opened, capacitor C holds the sampled voltage. To prevent loading of the capacitor C that would distort the sampled voltage, a high-impedance buffering amplifier 105 isolates the capacitor C from the remaining components of A/D converter 100 and provides a buffered sample voltage 102.
Sampled voltage 102 is then processed by a first stage and a second stage. The first stage includes a coarse-quantizing A/D converter that receives the sampled voltage from the sample-and-hold circuit to produce a coarsely-digitized signal 110. The coarsely-digitized signal 110 is converted back into an analog voltage 120 in the first stage by a digital-to-analog converter (DAC). The second stage includes an amplifier 110 configured to provide the difference between sampled voltage 102 and analog voltage 120. This difference is digitized in a fine-quantizing A/D converter to provide a digitized version 140 of the difference signal. By combining digitized signals 140 and 110, a digitized voltage sample is provided. The sample rate of this simple two-stage approach is limited by the need to capture a sample, perform the coarse conversion, analog reconstruction, subtraction, and fine conversion all within one sample period. In this fashion, the single sample-and-hold circuit is available to capture the next sample. More complex subranging A/D converter architectures cascade multiple sample-and-hold circuits so that part of the conversion can take place after the converter has begun to acquire the next sample. Although these more complex subranging A/D converter architectures can accommodate higher sampling rates, this accommodation comes at the cost of increased complexity, power dissipation, and loss of accuracy as the sample information is transferred from one sample-and-hold circuit to the next in the cascade.
Although two-stage subranging A/D converter 100 avoids the excessive components necessary in a flash architecture and the excessive pipelining of a pipelined architecture, it too suffers from a number of disadvantages. For example, because the sample-and-hold circuit is directly sampling the input voltage through a voltage switch, it usually requires some type of feedback with respect to the voltage switch to provide adequate input-to-output isolation. This feedback becomes difficult to implement at higher throughput speeds. Moreover, the buffer amplifier must accommodate the entire dynamic range of the input voltage. Designing such a buffer amplifier for high throughput speeds while still maintaining low-noise, low-distortion, and fast settling times becomes problematic.
Accordingly, there is a need in the art for improved subranging A/D converter architectures.